Components in digital systems typically operate using a system clock. A system clock provides synchronization to digital circuits in the components to allow the circuits to generate and process information. At various times, different components in a digital system may use clock signals with different frequencies and/or duty cycles. Although multiple clocks may be included in a system to generate clock signals with different frequencies and/or duty cycles, multiple clocks in a system may add cost, complexity, or physical space to a design of the system. As a result, the use of multiple clocks to generate clock signals with different frequencies and/or duty cycles in a digital system may be undesirable.
Various analog or digital circuits may be used to alter the frequency or the duty cycle of a clock signal. These circuits, however, may not provide a clock signal that has a desired frequency and/or duty cycle for a particular digital system. For example, the circuits may not generate a divided clock signal with a 50% duty cycle where the divided clock signal has a frequency that is an odd fraction of the frequency of the system clock (e.g. ⅓, ⅕, {fraction (1/7)}, etc.). In addition, these circuits may not be programmable such that the frequency of a clock signal may be changed at various times.
It would be desirable to be able to generate a clock signal that has a frequency that is a fraction of a frequency of another clock signal.